Intel announced a breakthrough in Moore’s Law!
Tenfold increase in the interconnection density of multi-chip packages, and the introduction of two-dimensional materials into chips!
Recently on December 12, According to a report by tech publication VideoCardz, Intel has published an article announcing three new technologies that break Moore’s Law. The goal of these technologies is to enable chip technology to continue to develop after 2025 when significant reductions in process sizes have already been achieved.
At the IEEE International Electronic Equipment Conference in 2021, Intel announced a 10-fold increase in the interconnect density of multi-chip hybrid packages, a 30%-50% increase in transistor density, new power and memory technologies, and quantum computing chip technologies amongst other things.
Intel elaborated on some of the innovative technologies that have been announced so far, including Hi-K metal gates, FinFET transistors, RibbonFETs, etc. In the roadmap, Intel also showed a variety of chip processes, including the Intel 20A process, which further reduced the volume of logic gates, called Gate All Around.
The following things were the focus of Intel’s report:
Table of Contents
1. Intel’s new 3D stacking, multi-chip packaging technology:
This technology is applied to the scenario of a variety of chip hybrid packaging, which can combine chips with different functions and different manufacturing processes in an adjacent or stacked manner. Foveros Direct technology increases the density of connection points between the upper and lower chips by 10 times, and the pitch of each connection point is less than 10 microns.
This technology supports the close integration of CPU, GPU, and IO chips, and it is also compatible with mixed packaging of chips from different manufacturers.
Officials from Intel said that this program has a high degree of flexibility, allowing customers to flexibly customize chip combinations according to different needs. In addition, Intel calls on the industry to develop a unified standard to facilitate the interconnection between different chips.
Intel demonstrated RibbonFET’s new transistor architecture in July 2021 as an alternative to FinFET. The new packaging method can stack NMOS and PMOS together and closely interconnect, so as to increase the transistor density of the chip in space. This method can increase the density of transistors by 30% to 50% under the inconvenience of the manufacturing process and continue Moore’s Law which had seen some reduction in the past few years.
In addition, Intel also said that it can introduce two-dimensional materials into the manufacturing of chips. This can make the connection distance shorter and solve the physical limitations of traditional silicon chips. This two-dimensional material is a single layer of molybdenum disulfide MoS2, which can be applied to the silicon chip connection layer to reduce the pitch from 15nm to 5nm.
2. More efficient power supply technology and DRAM memory chip technology
At present, Intel has realized for the first time to manufacture CMOS chips with GaN gallium nitride switches on 300mm silicon wafers. This power technology supports higher voltages. The finished power management chip can control the voltage of the CPU more accurately and quickly, helping to reduce losses. In addition, this chip can also reduce the power supply components on the motherboard.
The right side of the picture above shows the low-latency memory technology developed by Intel: FeRAM. This type of chip introduces iron elements into chip manufacturing, which can greatly increase the read and write speed of the memory chip, completing the read and write within 2 nanoseconds. At the same time, FeRAM technology can increase the density of memory chips.
3. Quantum computing chips based on silicon chips are expected to replace MOSFET transistors in the future!
With the further increase in transistor density in the future, traditional silicon chips will reach their physical limits. At the IEDM 2021 conference, Intel demonstrated the world’s first logic device that realizes a magnetoelectric spin-orbit (MESO) at room temperature. This represents the possibility of manufacturing nano-scale quantum operation transistors.
Intel and IMEC are making progress in the research of spintronic materials and are expected to produce full-featured devices that can be mass-produced in the future. In addition, Intel also demonstrated the manufacture of 300mm wafer quantum computing circuits compatible with current CMOS chips and established future research directions.
So guys are you excited about the future of Silicon and processors in general? Do let us know your thoughts in the comments section below! Feel free to subscribe to our Inspire2Rise newsletter in order to receive more such tech articles on a timely basis!
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