On April 25, 2024, TSMC announced in its annual report that the N2 process node with a backside power supply is scheduled to be introduced to customers in the second half of 2025, with mass production expected in 2026.
This version of the N2 process will incorporate GAA technology using a Nanosheet structure, which significantly improves performance and energy efficiency, with mass production slated to start in 2025.
The backside power rail version of the N2 process is deemed most suitable for high-performance computing applications. Unlike traditional chip manufacturing, which builds from the bottom up—first creating transistors and then the interconnect and power supply layers—this method grows increasingly complex as process technology scales down, interfering with design and manufacturing.
Moving the power supply network to the back of the wafer simplifies the power delivery path, alleviates interconnect bottlenecks, and reduces power supply interference with signals, ultimately decreasing overall platform voltage and power consumption.
TSMC’s major competitors in advanced process foundries, including Intel and Samsung, are also actively exploring backside power supply technologies.
Intel is set to introduce backside power supply in its Intel 20A node in the first half of this year, while Samsung is expected to implement this technology in its SF2 node by 2025.
The 2nm process node marks a significant milestone as it brings backside power supply into commercial use.
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