TSMC’s N4C Process Set for 2025 Launch: Cost Reductions up to 8.5% Compared to N4P

TSMC plans to introduce the N4C process in 2025, enhancing their 4nm production line with cost reductions and improved design efficiency.

TSMC recently showcased its new 4nm production process named N4C, aimed at significantly lowering costs and optimizing design efficiency to enhance its 5nm production technologies.

During the 2024 North American Technology Symposium, TSMC’s Vice President of Business Development, Kevin Zhang, discussed ongoing improvements in transistor performance and density scaling from N5 to N4 technologies.

“Our 5nm and 4nm process cycle is not over yet, with optical shrink density improving by 4% from N5 to N4, and we continue to enhance transistor performance.

We are now introducing the N4C process for our 4nm technology lineup, enabling our customers to eliminate some masks and improve original IP designs such as standard cells and SRAM to further reduce the total product-level cost of ownership.”

tsmc n4c production soon

The N4C process, building on the N4P technology, offers cost reductions of up to 8.5% by redesigning standard cells and SRAM units, modifying design rules, and reducing the number of masks used.

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TSMC’s N4C Process Set for 2025 Launch: Cost Reductions up to 8.5% Compared to N4P

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