According to WCCFTECH news reports, early in the Skylake microarchitecture release, Intel began to adjust the structure of its CPU cache in HEDT series processors. Now according to Geekbench, Intel’s forthcoming 10nm Tiger Lake mobile processor will undergo similar cache structure adjustments.
According to reports, in the Skylake-X HEDT processor, Intel reduced the L3 cache and increased the low-latency L2 cache. In Tiger Lake-Y series processors, Intel may bring comprehensive improvements in L1, L2 and L3 caches. Previously, mobile and desktop CPUs used the same cache structure, but by redesigning the cache, Intel plans to increase the efficiency of mobile CPUs.
According to Geekbench, Tiger Lake-Y has 4 cores and 8 threads. The main feature of this chip is that the cache structure has been greatly changed. Each core has 1,280KB of L2 cache, and the total L2 cache has reached 5,120KB, which is a 400% improvement over the previous generation. In addition, the L3 cache also has a total of added 12MB.
In terms of L1 cache, Intel has increased the size of the L1 instruction cache to 48KB, but the L1 data cache is still 32KB. Multiple tech media have predicted that Tiger Lake is expected to bring new features of PCIe 4.0 and Intel Xe core display.
So guys what do you think? Will the Intel TigerLake processors be a huge jump in performance from the existing chips? Do let us know your thoughts in the comments section below! You can also subscribe to the Inspire2Rise newsletter and our push notifications to get more timely tech updates and leaks daily!
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