According to reports on September 10, AMD’s fifth-generation EPYC processor, codenamed “Turin,” will utilize the current SP5 platform, consistent with AMD’s strategy of using the same socket for two generations of server CPUs.
The forthcoming processor, “Venice,” is anticipated to employ the novel SP7 platform. As disclosed by @YuuKi_AnS, a user formerly affiliated with Twitter, AMD’s most recent data center roadmap reveals that the company’s sixth-generation EPYC processor carries the codename “Venice.”
Based on AMD’s cutting-edge Zen 6 core technology, this family of processors will leverage the SP7 socket, slotted to succeed the existing SP7 platform.
The claimant assured us that the improved platform would offer up to 16 memory channels, accommodating both DDR5 and innovative memory varieties (such as MR-DIMM and MCR-DIMM). Even with numerous cores, the new processor can guarantee adequate memory bandwidth, thanks to the platform’s design.
In light of the increased core count, substantial improvements in power delivery capabilities are projected for the SP7 platform when paired with the Venice processor. Bearing in mind that the SP5 platform’s peak power supply capacity reaches 700 W; it’s plausible that AMD’s sixth-generation EPYC processors might experience tangible advancements in performance.
While our understanding of the SP7 processor remains limited, speculation suggests that it will likely feature an expanded pin count exceeding SP5’s 6096 pins, potentially necessitating a more extensive CPU package. Such modifications would allow for an increase in both cores and functionality.
AMD Known Platform Specifications
|code name||7003 “Milan(-X)”||9004 “Genoa(-X)” 8004 “Bergamo” 8004 “Siena”||9005 “Turin(-X)” 8005 “Turin-Dense”||9006 “Venice”|
|platform||SP3 (LGA4094)||SP5 (LGA-6096) SP6 (LGA 4094)||SP5 (LGA-6096) SP6 (LGA 4094)||SP7|
|Memory||8C DDR4||12C DDR5||12C DDR5||16C DDR5|
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